｜ Contest Overview:
The Synopsys ASIP Designer Contest aims to foster innovation and hands-on learning among students in the fields of AI, RISC-V, and custom processor design. This year's contest focuses on using AI models from MLPerf to benchmark students' work, showcasing their ability to leverage Synopsys ASIP Designer for RISC-V and AI accelerator design. Participants will apply their skills in developing custom processors optimized for AI workloads, benchmarking their designs against industry standards.
｜ Host: Synopsys
｜Co-Host:
- Taiwan Semiconductor Research Institute (TSRI)
- RISC-V Technology and Innovation Applied Teaching Materials Development Program, Ministry of Education
｜ Contest Theme:
Creating extended instructions on the RISC-V CPU through ASIP Designer to accelerate AI models of the MLPerf TinyML benchmark.
｜ Objectives:
- Help academic users leverage ASIP Designer in creating application-specific instruction set processors (ASIPs) for RISC-V and AI accelerators.
- Provide a platform for academic users to demonstrate their knowledge in AI, processor architecture, and hardware-software co-design.
- Connect academic users with industry standards and emerging trends in AI and processor design.
｜ Eligibility:
- The contest is open to undergraduate and graduate students enrolled in an engineering, computer science, or related program at an accredited university in Taiwan.
- The contestants should form a team to sign up for the contest. The team should consist of at least 1 student and a maximum of 3 students.
｜ Contest Phases:
Registration and Preparation
- Participants must register for the contest. The team leader should submit the registration on behalf of all team members.
- Participants should self-study the resources provided by Synopsys as identified in below section “Recourses Provided”.
- Participants need to follow the instructions identified in the section “Resources Provided” to apply for access to Synopsys ASIP Designer and license setup.
Phase I – Contest Submission
- The contest topic will be released on Sept. 27 at the end of the training workshop.
- During this phase, participants will design their RISC-V processor, optimizing it for the selected AI workloads from MLPerf TinyML benchmark (https://github.com/mlcommons/tiny).
- Participants must document their design process, including challenges, innovations, and design decisions.
Phase II – Final Contest, Presentation and Announcement of Winners
- Top 8~10 teams will be selected as finalists into Phase II and present their works to a panel of judges, including experts from Synopsys, academia, and the semiconductor industry.
｜ Judging Criteria:
Phase I – Contest Submission:
- Performance of their RISC-V processors on AI models of the MLPerf TinyML benchmark: cycle count, instruction count, and correctness of AI models’ output.
- When passing golden test, the cycle count takes 80% and instruction count takes 20% of the entire score. Otherwise, the result won’t be considered.
Phase II – Final Contest (Contest Team Presentation):
- Benchmarking Results: Consider gate count and PPA after synthesizing the submitted RISC-V processor and other performance metrics obtained in Phase I.
- Innovation and Creativity: Originality of the design and approach to solving the problem.
- Technical Competence: Depth of understanding and application of RISC-V processor, and Synopsys ASIP Designer.
- Presentation: Clarity, organization, and ability to communicate the project effectively.
- Documentation: Quality and thoroughness of the design documentation and final presentation.
｜ Prizes:
Prizes are sponsored by Synopsys. Certification will be rewarded by Synopsys, TSRI and RISC-V Technology and Innovation Applied Teaching Materials Development Program of the Ministry of Education.
- First Place: NT$50,000 and a Certification.
- Second Place: NT$30,000 and a Certification.
- Third Place: NT$15,000 and a Certification.
- Honorable Mentions: NT$8,000 and a Certification.
Winning teams will be invited to Synopsys AIoT Summit to receive the awards.
｜ Timeline:
- Registration Deadline: Sept. 27, 2024
- Training Workshop (hybrid) & Announcement of Contest Topic: Sept. 27, 2024
- Contest Submission Deadline: Nov. 3, 2024
- Contest Review Deadline: Nov. 8, 2024
- Final Contest, Presentation and Announcement of Winners: Nov. 14, 2024
- Award Ceremony at Synopsys AIoT Summit: Nov. 19, 2024
｜ Resources Provided:
- Access to Synopsys ASIP Designer software through TSRI. Please follow the application flow to get the license accessing grant (https://www.tsri.org.tw/tw/commonPage.jsp?kindId=D0009) and download the ASIP Designer (https://etas.tsri.narl.org.tw/eda/edaCustomer/SoftwareInfoByVendor), Select "Synopsys -> ASIP Designer".
- Online tutorials and self-learning resources are provided by Synopsys (Please download via 【File Download】on this website).
- Training Workshop (hybrid) on ASIP Designer on Sept. 27. Details will be announced later to the registrants.
- Support from contest experts through forums and Q&A sessions on Slack. You will receive a Slack invitation link after registration for the Contest.